1. Field of the Invention
The present invention relates to a method for designing a semiconductor device. More particularly, the present invention relates to a method for designing a semiconductor device using a computer, in which a semiconductor device is designed so as to control a power supply variation due to reset. The invention also pertains to a semiconductor device designed by this method.
2. Description of the Related Art
A memory circuit such as a flip-flop has a function of keeping data. Therefore, in a semiconductor device such as an LSI (Large Scale Integration) having the memory circuit, the circuit must be first set to an initial state before starting an operation or a test.
The semiconductor device has a terminal and a reset line. The terminal resets the memory circuit on a semiconductor chip. The reset line is connected from the terminal to a reset terminal of each memory circuit. In this device, when a reset signal is sent from the terminal, the memory circuit can be initialized. A design method of this semiconductor device in which the memory circuit can be reset is performed using a computer as follows.
FIG. 7 is a flow chart showing a conventional method for designing a semiconductor device.
In step S101, the computer arranges macros such as an SRAM (Static Random Access Memory), a RAM (Random Access Memory) or a PLL (Phase Locked Loop) on a semiconductor chip on the basis of inputted arrangement information.
In step S102, the computer wires power wires on the semiconductor chip on the basis of inputted wiring information.
In step S103, the computer arranges cells on the semiconductor chip on the basis of inputted arrangement information. The cells are, for example, a logic circuit such as an AND circuit, an OR circuit or a flip-flop (a memory circuit) comprising these circuits.
In step S104, the computer wires clock lines on the basis of inputted wiring information. The clock line provides the cell with a clock, for example, for operating the cell in synchronization therewith.
In step S105, the computer wires reset lines for all the memory circuits to be reset.
In step S106, the computer wires data lines on the basis of inputted wiring information.
In step S107, the computer adjusts the timing so that the semiconductor device can properly operate. For example, the computer inserts buffers between wirings so that an operation timing of each circuit can be adjusted.
Further, there is disclosed a semiconductor integrated circuit in which a peak current during reset is controlled so that noise appearing on the power supply voltage and the ground voltage can be reduced and generation of the latch-up phenomenon can be prevented (see, e.g., Japanese Unexamined Patent Publication No. Hei 08-008706).
However, in the conventional method for designing a semiconductor device, all the memory circuits to be reset are simultaneously reset. Therefore, this design method has a problem that when resetting all the memory circuits simultaneously, a large current flows to cause large AC (Alternating Current) noise in a power supply and as a result, the semiconductor devices may be broken.